A semiconductor device such as a large scale integrated circuit (LSI) or a metal oxide semiconductor (MOS) transistor is manufactured by performing a processing such as doping, etching, chemical vapor deposition (CVD) or sputtering on a semiconductor substrate (a wafer) which becomes a processing target substrate.
Here, as a method of performing a doping, there are an ion doping method using an ion implanting device, and a plasma doping method of directly implanting radicals or ions of dopant into the surface of a processing target object using plasma. A request for a method of uniformly implanting dopant impurities into a doping target having a three-dimensional structure, such as a Fin-type field effect transistor (FinFET-type) semiconductor device, irrespective of uneven portions of the three-dimensional structure (a conformal doping method), has recently been highly increased. As a result, numerous attempts on a doping method using plasma have been reported.
For example, a doping method (a plasma doping method) using a doping processing device employs a technology in which ionic plasma is mainly produced and then the produced ionic plasma is distracted to perform doping on the entire three-dimensional structure.
As a recently attempted method of uniformly implanting dopant ions into a side wall of a FinFET-type semiconductor device, a method called ion assisted deposition and doping (IADD) in which dopant ions are conformally implanted into the side wall of the FinFET-type semiconductor device has been introduced. The IADD is a method of additionally performing ion slant irradiation on an As (arsenic) film formed using plasma.
Here, when doping is performed on a doping target having a three-dimensional structure, such as a FinFET-type semiconductor device, there is a background in that respective portions of the doping target are required to have a high coatability, that is, a high conformality (uniformity) in doping such that doping depths from the surfaces of the respective portions or dopant concentrations are uniform. In relation to this, see, for example, non-patent literatures 1: K. Han*, S. Tang, T. Rockwell, L. Godet, H. Persing, C. Campbell, S. Salimian, Junction Technology (IWJT), 2012 12th International Workshop on, Date 14-15 May 2012, IEEE, and 2: Y. Sasaki, L. Godetl, T. Chiarella, D. P. Brunco2, T. Rockwelll, J. W. Lee, B. Colombeaul, M. Togo, S. A. Chew, G. Zschaetszch, K. B. Noh3, A. De Keersgieter, G. Boccardi, M. S. Kim, G. Hellings, P. Martinl, W. Vandervorst, A. Thean, and N. Horiguchi, “Improved Sidewall Doping of Extensions by AsH3 Ion Assisted Deposition and Doping (IADD) with Small Implant Angle for Scaled NMOS SiBulk FinFETs”, proceeding IEDM 2013, IEEE.